In the development of integrated circuit (IC) technologies, there is continuous pressure to reduce size and power consumption of the IC, and at the same time increase performance. To achieve these goals, three dimensional integrated circuit architectures have been developed to facilitate miniaturization and shorten interconnection between different ICs. Three dimensional ICs include two or more ICs that are arranged in multiple layers that are interconnected vertically in order to occupy less space and reduce propagation delay between the two or more ICs. The multiple layers may be epitaxially grown, or fully processed ICs can be bonded together for vertical integration.
In many three-dimensional ICs, the IC layers are interconnected with wiring along their edges. However, as semiconductor technology has advanced, the amount and speed of logic available on an IC has increased more rapidly than the number and performance of input/output (I/O) connections. Additionally, because each interconnection must be routed to the edge, signal line lengths are increased, and the number of interconnections may be limited. An interposer layer is often included between each IC layer to perform interlayer routing. The interposer routing further increases interconnection wiring length.
A more recent trend is to replace edge wiring of each IC layer with vertical connections through the body of the stacked ICs. These vertical interconnections are referred to as through silicon vias (TSVs). To form a TSV, a hole is etched through the silicon body of the IC and filled with a conductive material such as copper. The conductive material is surrounded by a dielectric barrier. Through the use of TSVs, interconnects between the IC layers may be shortened, allowing reduced timing delays, faster clock speeds, and reduced power consumption.
Although TSVs allow signal line lengths to be reduced between layer interconnect points, transmission delays may result from parasitic capacitance and inductance exhibited by the TSV interconnections. As distances the multi-layered interconnection structure increase, parasitic capacitance and parasitic impedance induced by the TSV become more significant. At high clock speeds, performance is affected by parasitic resistance and capacitance introduced by TSVs. The effect of parasitic resistance on performance degradation is minimal. However, unless properly designed, the parasitic capacitance of a TSV can have significant impact on I/O performance.
The embodiments of present invention may address one or more of the above issues.